VERIFICATION
METHODOLOGIES
TODAY
TECHNOLOGY
& SOLUTIONS
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VERIFICATION METHODOLOGIES TODAY
Verification today is a central component of
modern electronic design methodologies, and arguably the single most
risky and intensive part of the entire process. Yet, drawing the
conclusion that enough verification has been performed on a design
still requires an unscientific, gut instinct call on behalf of project
managers, leaving the potential for bugs to exist deep within the code
structure, only to be discovered after chip fabrication.
Given
the astronomical and escalating costs, not to mention time-to-market
impact, of a device re-spin resulting from an unearthed, errant bug,
concern about the effectiveness of verification processes have permeated
the entire industry. Indeed, fundamental and expensive shifts in
electronic product architectures, towards less risky software-based
functionality on proven processor platforms, have resulted partly from
the lack of confidence in correct first time hardware design capability.
Functional verification methodologies have evolved dramatically
over the last fifteen years. From HDL simulation based environments with
directed tests written by the designers, to approaches leveraging
constrained random test generation based on design specifications, and
utilized by specialized teams, verification productivity improvements
are continuously driven by design size and complexity.
The
principle manner in which verification confidence is assessed today is
through the use of various verification coverage metrics. However, these
metrics often do not provide a clear indication of actual coverage
achieved, leaving project managers to estimate verification quality
based on other factors, such as the last time a bug was discovered, and
the number of tests run. As the cost of inadequate verification is high,
the tendency is for project teams to apply many more tests than required
in an effort to saturate the designs with wide ranges of operational
scenarios. The overlap between test sets, estimated as high as 5X in some
cases, results in wasted simulation cycles and engineering time.
This
is further compounded by the fact that some coverage areas within the design
are extremely hard to reach, particularly when utilizing a constrained random
test generation approach. Without leveraging information about the design
structure itself, it is likely that the verification process will miss
these areas all together, increasing the risk of a faulty design making it
through into production.
Verification technologies have been proposed
to aid in this effort. However, these suffer from either an impractical
compute resource requirement (e.g. Formal Verification), require a wholesale
overhaul in methodology, or an extensive new language learning curve. These
are not options for already overstressed verification teams.
The
potential impact on electronic design today of increasing verification
confidence, tracking hard to reach design areas, and eliminating test
redundancy in an automated, practical, and easy to apply fashion cannot be
overstated.
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